This invention relates to the application of precision delay circuits in integrated circuit memories to obtain a high operating speed and low power dissipation.
In the prior art, delay circuits have been conventionally structured in an integrated circuit chip as a serial string of several inverter gates. This is illustrated in FIG. 1 by the serial string of N inverters 10-1 through 10-N. Each of the inverters is comprised of a P-channel transistor 10a and an N-channel transistor 10b; and these two transistors are shown in FIG. 1 only for the first inverter 10-1 in order to simplify the drawing.
In operation, a digital input signal v.sub.i is applied to an input terminal 10c of the first inverter 10-1. Then signal v.sub.i is high, transistor 10a is off and transistor 10b is on; whereas when signal v.sub.i is low, transistor 10a is on and transistor 10b is off. Thus, any low-to-high transition (or high-to-low transition) in signal v.sub.i sequentially switches the on/off state of the transistors 10a and 10b in each of the inverters to thereby generate an output signal v.sub.o which is a delayed replica of the input signal v.sub.i. To increase the delay between the input signal v.sub.i and the output signal v.sub.o, the total number N of inverters is increased; and vice-versa.
Also in the prior art, the above-described serial string of inverter gates is conventionally used in conjunction with an AND gate 11 to generate a pulse signal v.sub.p. In the case where the total number of inverters N is odd, the pulse v.sub.p begins when the digital input signal v.sub.i makes a low-to-high transition; and that pulse v.sub.p lasts until the input signal transition propagates through the last inverter 10-N.
However, a major problem with the FIG. 1 circuits is that the delay in the output signal v.sub.o and the width of the pulse signal v.sub.p has a large tolerance. Such a large tolerance occurs because on any one particular integrated circuit chip, the transistors 10a and 10b in the inverters 10-1 through 10-N switch on and off at an unpredictable speed. This is illustrated by a graph in FIG. 2 wherein a range of switching speeds is given on the horizontal axis, and the corresponding probability for any particular switching speed to occur in the transistors 10a and 10b is given by a curve 12.
Inspection of curve 12 shows that the transistors 10a and 10b on any one particular chip have an unpredictable switching speed which can be anywhere between the slowest speed 13a to the fastest speed 13b. In other words, the switching speed of the transistors 10a and 10b has a tolerance .DELTA..sub.1 which occurs about a mean speed 13c that lies midway between the slowest speed 13a and the fastest speed 13b. This switching speed tolerance .DELTA..sub.1 arises due to certain unavoidable variations in the process by which the transistors 10a and 10b are fabricated. Two such process variations are identified in FIG. 2 by reference numeral 14 as variations in the transistor's gate length and variations in the thickness of the transistor's gate oxide.
Due to the large switching speed tolerance .DELTA..sub.1 of FIG. 2, the delayed output signal v.sub.o and the pulse output signal v.sub.p are generated with a proportionately large tolerance k.DELTA..sub.1 as shown in FIG. 3. Signal v.sub.o occurs with a minimum delay 15a, a maximum delay 15b, and a mean delay 15c which respectively correspond to the switching speeds 13a, 13b, and 13c. Similarly, the output pulse v.sub.p occurs with a minimum width 16a, a maximum width 16b, and a mean width 16c which respectively correspond to the switching speeds of 13a, 13b and 13c.
In order for the delayed output signal v.sub.o to occur with precision, the delay tolerance of k.DELTA..sub.1 must be small in comparison to the mean delay 15c. Likewise, in order for the pulse output signal v.sub.p to have a precise width, the width tolerance of k.DELTA..sub.1 must be small in comparison to the mean width 16c. Unfortunately, however, the process variations 14 become more and more significant as the physical size of the transistors 10a and 10b get smaller and smaller. For submicron transistors having a mean size of 0.50 .mu.m, the delay tolerance k.DELTA..sub.1 is about 90% of the mean 15c.
Accordingly, one object of the invention is to provide an integrated circuit memory which incorporates a novel delay/pulse generating circuit to achieve a faster operating speed than the prior art.
Another object of the invention is to provide an integrated circuit memory which incorporates a novel delay/pulse generating circuit to achieve a smaller power dissipation than the prior art.